An inner pc aided design (CAD) or design companies engineer is answerable for delivering environment friendly, sturdy and high-quality design circulation options. The design circulation on a day-to-day foundation retains chip designers and verification engineers productive and targeted on their jobs, stopping them from debugging CAD instruments and flows and creating advert hoc and undocumented scripts. Over the lifetime of a undertaking, a high-quality design circulation differentiates an organization from opponents and may be the distinction between getting chips to market first or being the sufferer of surprising course of bottleneck and delays.
And but, each semiconductor undertaking group offers with inefficiencies that constrain them from delivering supreme options and limits productiveness. At present’s CAD engineers use a patchwork of instruments, flows and scripts consisting of business digital design automation (EDA) merchandise, business or in-house personalized add-ons and in-house mental property (IP), an issue for a lot of undertaking teams due to:
- Instrument circulation gaps in present EDA merchandise
- The burden of sustaining in-house or homegrown instruments, flows and scripts
- The dearth of time to construct and take a look at high-quality, sturdy inner instruments
That inevitably results in a bunch of issues, as defined within the following sections.
Limitless script design loops
The burden of sustaining in-house or homegrown instruments, flows and scripts is considered one of cascading interventions. It could begin out with a design engineer writing a Perl or Tcl script to beat a roadblock within the design verification course of.
Because the undertaking group makes use of it, particular circumstances and features don’t work. The script will get one other rework to refine it and will get handed as much as the chip lead for evaluation who notes enhanced automation, then notices that the script doesn’t deal with one thing essential.
Extra points come up as extra of the undertaking group makes use of the script. The script will get handed to the inner CAD group for ongoing assist and upkeep. Extra points come up as the inner CAD division begins to make use of it. CAD spends three weeks engaged on the script to deal with these points and ongoing upkeep requires sooner or later per week.
It’s not lengthy earlier than assist and upkeep of 1 inner script prices between $50,000 and $100,000 per yr. In the long run, the script was required for the event course of, however the monetary and undertaking time price is excessive and unpredictable.
The burden of upkeep consists of making certain present inner instruments and flows proceed to work. Different upkeep choirs might be including options to present inner instruments and flows, and shifting to a brand new {hardware} description language (HDL), reminiscent of Verilog to SystemVerilog, or including assist for a further HDL as a result of third-party IP. The estimated price of updating only one in-house Perl or Tcl script to assist SystemVerilog may be $175,000 and 6 months of undertaking time.
Time is the enemy
An organization’s main purpose is to get the silicon machine to market quick. The CAD division’s job is to assist the designers and verification engineers, which suggests persevering with to prop up the patchwork of instruments, flows and scripts hybridized from business EDA merchandise and in-house IP.
The dearth of time to construct sturdy instruments is an issue. A CAD engineer is aware of what she or he needs a software to do, is aware of design, implement and take a look at it, however doesn’t have the time to do it.
Homegrown fixes embrace:
- Turning to open-source parser tasks, although they by no means have the complete language protection or assist for brand spanking new constructs.
- Rewriting inner flows and scripts and utilizing extra sturdy software program engineering methodologies, a troublesome job to justify the sources to “re-do” work.
- Switching from Perl or Tcl to Python for higher understandability and performance. This doesn’t resolve HDL complexity—the SystemVerilog language reference guide (LRM) is 1,300 pages of complicated specs.
- Jury-rigging present business EDA instruments to carry out duties they weren’t meant to do typically finally ends up with unsatisfactory outcomes and a dependency on costly licenses.
On the similar time, the undertaking group is taking an enormous danger if CAD is unable to persistently ship best-in-class design and verification flows. Lacking market home windows and/or delivering silicon that’s not aggressive may be deadly to a semiconductor firm given the brand new product cycles and excessive prices of IC growth.
Options exist and vary from in-house growth of {custom} instruments to buying a personalized software constructed by an EDA firm, with variations in between.
4 methods to construct best-in-class CAD flows
One
Creating sturdy, high-performance CAD instruments in-house would yield a license-free, proprietary software that might be the key weapon to reliably get a chip to market first. It could require constructing a parser from scratch to detach from any licensing agreements.
Disadvantages are:
- It may be extraordinarily time consuming.
- It requires a deep understanding of HDL languages and the way they’re used.
- Outcomes is probably not sturdy as a result of the underlying infrastructure is weak and untested.
- The software might have insufficient testing, resulting in an iterative assist mannequin.
- It could not observe new developments in HDL languages.
- Deployment time might be lengthy, starting from one yr to a number of years.
Two
License a C++ parser library and rent a software program growth group to construct {custom} CAD instruments that bypass present limitations. This resolution is an outsourced variation of the earlier one. Commercially obtainable parsers provide advantages, together with full-language protection for VHDL, Verilog, SystemVerilog and UPF.
Inner CAD teams are sometimes extra skilled in scripting fashion languages reminiscent of Perl, Tcl and Python and will not have the depth of growth experience in C++. The C++ library may be troublesome to make use of with out in depth C++ software program growth experience.
Three
Ask an EDA vendor to {custom} construct options/perform wanted to allow a design circulation. A bonus of this resolution can be assist and upkeep of the requested functionality if it’s built-in into the mainline of the product. A consulting undertaking by the EDA vendor would imply the duty for added ongoing consulting companies to take care of the characteristic/perform.
What’s extra, the corporate can be beholden to the EDA vendor’s schedule or the seller might not construct or be capable of construct the customization. The EDA vendor might require upfront cost for non-recoverable engineering (NRE) prices and, if the EDA vendor provides requests to its subsequent launch, a personalized characteristic or perform turns into obtainable to opponents. Moreover, if the EDA vendor builds a personalized software, there will likely be ongoing obligations for IP points and licensing necessities.
As well as, relying on the character of the undertaking and engagement, the EDA vendor might present the requested performance to its different clients, thereby shedding any aggressive benefit related to the options/perform. Many EDA distributors additionally present utility engineering assist for customizing their software integration into their clients’ flows. As a result of this kind of experience is often offered to different main licensees, it’s not prone to impart a aggressive benefit.
4
License a CAD software growth platform that accommodates built-in HDL parsers, industrial-quality databases and assist for traditional file codecs for in-house growth utilizing mainstream scripting environments. A platform resolution like that is meant for design, verification and CAD engineers to shortly create focused {custom} purposes for semiconductor design and verification.
A strong, high-performing and easy-to-use CAD software growth platform ought to:
- Present full parsing of Verilog, SystemVerilog, Verilog-AMS, VHDL, Liberty and UPF.
- An intuitive API with a language acquainted to a {hardware} engineer reminiscent of Python that abstracts complexity and permits particular management when wanted.
- Be pre-tested on a big set of benchmarks that show typical use circumstances and the entire HDL language behaviors, together with constructs and use circumstances.
- A assist mannequin that describes utilizing the software and entry to consulting companies to complement growth.
- Totally operational pattern purposes simply modified for a consumer’s particular case.
CAD software growth platform
The largest problem that inner teams face is getting access to sturdy, easy-to-use and preserve and frequently supported HDL parsing environments. A CAD software growth platform offering each ease of use and sturdy capabilities would free the group from the bounds of business EDA flows whereas providing capabilities to distinguish its design circulation. Extra advantages are price financial savings on EDA software licenses, time financial savings in CAD instruments, circulation and script growth and elevated productiveness for design, verification and CAD engineers.
The CAD software growth platform would require an upfront funding, slightly than making use of free scripting instruments like Perl and Tcl, a downside that must be thought of. With the transfer from Verilog to SystemVerilog, for instance, easy Perl or Tcl scripts should not possible as a result of extra complexities of the language. A CAD software growth platform designed for HDL exploration and modification will allow new and progressive instruments and flows not doable utilizing general-purpose text-parsing capabilities.
A CAD software growth platform is an funding that permits totally utilized human capital; beneficial R&D sources fascinated with constructing the perfect ICs, not combating to debug advert hoc Perl scripts.
One other downside is the query of robustness of the parsing functionality for SystemVerilog, VHDL or UPF. To achieve success, the platform have to be primarily based on a extensively used and examined HDL parser library. With out it, every new design or undertaking will reveal extra limitations of the parser. Solely parsers actively utilized by 1000’s of engineers and actively maintained can deal with arbitrary new designs.
Closing gaps in a CAD circulation and getting off the limitless cycle of script design and debug, a licensed CAD software growth platform supplies the potential to leverage commercial-grade HDL parsers whereas simplifying their use.
Daniel Hoggar is a senior member of technical workers at Verific Design Automation.
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